1. Field of the Invention
The present invention relates to a limiter circuit for limiting an output signal level to a predetermined range.
2. Description of Related Art
In recent years, along with miniaturization and higher integration of devices in LSI, there are increasing number of circuits that operate with low voltages. Further, several circuits with different operating voltages are often mounted to one LSI. In such case, if an overvoltage more than a specified operating voltage is applied to a circuit that operates with a low voltage, the circuit may be destroyed as the overcurrent flows through the circuit. Accordingly, when outputting a signal from a circuit that operates with a high voltage to a circuit that operates with a low voltage, a voltage level of an output voltage must be limited by a limiter circuit.
FIG. 10 is a configuration example showing an apparatus including two circuits that operate with different voltages and a limiter circuit. In FIG. 10, a first circuit 1 is a circuit operating with a power supply voltage VDD1. A second circuit 2 is a circuit operating with a power supply voltage VDD2. A limiter circuit 3 takes an output voltage from the first circuit 1 as an input signal, where the output voltage from the first circuit 1 fluctuates within a voltage range from a ground level 0V to the power supply voltage VDD1, and limits a voltage level to the power supply voltage VDD2 or less so as to output to the second circuit 2.
FIG. 11 is a specific configuration example showing a first circuit 1. In FIG. 11, an input voltage VIN is applied to an inverting input of a differential amplifier 5, and an output from the differential amplifier 5 is connected to a gate of a Pch-MOS transistor MP1. A source of the transistor MP1 is connected to the power supply voltage VDD1. A drain of the transistor MP1 outputs an output voltage VOUT1 of the first circuit 1 and also is connected to a non-inverting input of the differential amplifier 5 and a constant current source 4. Another end of the constant current source 4 is connected to ground. With, this configuration, when the transistor MP1 is operated in a saturation region and a loop gain of the differential amplifier circuit 5 is large enough, a differential input voltage of the differential amplifier 5 becomes small and satisfies that output voltage VOUT1 is nearly equal to input voltage VIN.
As a configuration example of the limiter circuit 3, a configuration disclosed in Japanese Unexamined Patent Application Publication No. 58-70482 is shown in FIG. 12. In the limiter circuit 3 of FIG. 12, QL, QLL and QD are Nch-MOS transistors. An input voltage from the first circuit 1 is applied to an input terminal of the pulse generator 100. A non-inverting output of the pulse generator 100 is connected to a gate of the transistor QL. An inverting output of the pulse generator 100 is connected to a gate of the transistor QD. Further, a fixed voltage VLL is applied to a gate of the transistor QLL by a voltage converter 101. A drain of the transistor QL is connected to a power supply voltage VCC, and a source of the transistor QL is connected to a drain of the transistor QLL. Furthermore, a source of the transistor QLL is connected to the drain of the transistor QD, and a source of the transistor QD is connected to ground. Additionally, the drain of the transistor QD is output as an output voltage of the limiter circuit 3.
If the input voltage VOUT1 for the pulse generator 100 becomes a high voltage, a gate voltage of the transistor QD changes from a high voltage to a ground level by an operation of the pulse generator 100. Accordingly the transistor QD turns OFF and at the same time, the gate voltage of the transistor QL changes from the ground level to the power supply voltage level VCC. As a result, the transistor QL turns ON.
Here, as the constant voltage VLL is applied to the gate of the transistor QLL, if an output voltage VOUT2 exceeds VLL−VTH, the transistor QLL turns OFF. Accordingly the limiter circuit 3 operates so that the output voltage VOUT2 does not exceed VLL−VTH. Note that the voltage VTH is a threshold voltage of the transistor QLL.
Specifically, assuming a threshold voltage of the limiter circuit 3 that is determined by the transistors QL and QD to be VTQ, when the input voltage VOUT1 is higher than VTQ, the output voltage VOUT2 is limited to VLL−VTH. Further, when the input voltage VOUT1 is lower than VTQ, the output voltage VOUT2 becomes the ground level. FIG. 13 shows a relationship between the input voltage VOUT1 and the output voltage VOUT2.
FIG. 14 is a configuration diagram showing the limiter circuit 3 for limiting a voltage level of the output voltage using another method. In the limiter circuit 3 shown in FIG. 14, buffer circuits 200 and 201 output signals that are almost equal to input signals. Specifically, the buffer circuit 200 is disposed in order to increase an input impedance, while the buffer circuit 201 is disposed in order to decrease an output impedance. A resistance R functions as a current limit for preventing an overcurrent from flowing from the buffer circuit 200 to a voltage source 6.
In the circuit shown in FIG. 14, assuming a voltage value of the voltage source 6 to be VL and a forward voltage of the diode D to be VDT, when the input voltage VOUT1 is VL+VDT or less, the output voltage VOUT1 becomes almost same as the input voltage VOUT1. On the other hand, when the input voltage VOUT1 is more than VL+VDT, the diode D becomes forward bias and conductive. Accordingly the limiter circuit 3 of FIG. 3 operates so that the output voltage VOUT2 does not exceed VL+VDT.
However it has now been discovered that in the abovementioned limiter circuit tends to generate the output voltage including an error.
To be more specific, in the limiter circuit 3 shown in FIG. 12, the output voltage VOUT2 changes from the ground level 0V to a limited voltage VLL−VTH with the threshold voltage VTQ as a boundary that is determined by the transistors QL and QD. Accordingly the voltage level of the output voltage VOUT2 is limited to the ground level 0, which is a lower limit value, or VLL−VTH, which is an upper limit value. As described in the foregoing, the limiter circuit 3 shown in FIG. 12 is not able to output a middle voltage between the lower limit value 0V and the upper limit value VLL−VTH, thus when the input voltage is an analog signal, there is a problem that the input voltage cannot be correctly transmitted to an output side.
Further, as the limiter circuit 3 shown in FIG. 14 includes many devices, signal transmission errors can easily be generated caused by characteristic fluctuation of the resistance R, diode D, buffer circuits 200 and 201.